Adaptation of a HPC runtime system to FPGA

From a single chip to a supercomputer, heterogeneous architectures are everywhere.

Programming them is particularly challenging for application programmers without sacrificing efficiency, portability or ease of use. Based on the OpenMP standard, promising research projects have shown that these assets can be preserved. However, these execution frameworks are limited to heterogeneous architectures with CPU, GPU and/or accelerators like Xeon Phi. Despite excellent energy and performance capabilities, FPGA are poorly considered. FPGA are intrinsically very different from other kinds of hardware accelerators, and exploiting them at their full potential requires knowledge and skills HPC runtime designers rarely have. FPGA vendors are currently trying to encourage the scientific community to experiment with FPGA devices, proposing solutions to improve their accessibility.

With HLS tools, the entry point of FPGA design flow has raised to algorithm level instead of circuit level. HLS tools, such as AUGH, are even accessible to users that are not experienced with FPGA. Integrated inside an OpenMP compiler such as KSTAR, it can provide hardware tasks that can be managed by an heterogeneous runtime, making OpenMP applications benefit from FPGA devices.

The PhD thesis aims at adapting an existing heterogeneous HPC runtime system to support FPGAs.

The main goals are:

- the integration of FPGA tasks in the runtime system taking into account their singularities: coarser parallelism granularity, data management (communication, memory), configuration management

- the identification and exploitation in the runtime of valuable information (e.g. estimated execution time, configuration time, estimated power consumption), which can be gathered during the compilation of hardware tasks.